Phase locked loop (PLL) circuits are used in many types of electronic devices and systems. PLL circuits are typically used in devices to generate clock and other reference signals. Examples of applications that use PLL circuits include clock signal generation, clock sampling, signal synchronization, frequency synthesis, and so forth.
A conventional PLL circuit includes a phase detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), and a loop divider. For convenience, the designation PFD is used herein to refer generally to a phase detector or more specifically to a phase frequency detector. The PFD compares an input reference signal to an output signal generated by the VCO. Depending on the phase difference between the reference signal and the output signal generated by the VCO, the PFD controls the charge pump to charge or discharge a load capacitor within the loop filter. The charge on the load capacitor within the loop filter generates an output voltage, which is used by the VCO to generate the output signal. As the output signal is fed back to the PFD via the loop divider, the PLL circuit continues to adjust the charge on the load capacitor in the loop filter and, thereby, change the output signal to match the input reference signal.
Because the operation of the charge pump has a direct effect on the charge of the load capacitor in the loop filter, which influences the quality of the output signal that is generated, the operation of the charge pump can result in spurious noise in the generated output signal of the PLL circuit. Specifically, the charge pump can cause spurious noise in the output signal through charge injection, clock feed-through, and up/down current mismatch.
FIG. 1 depicts a conventional charge pump circuit 10. The illustrated charge pump circuit 10 includes two p-channel metal-oxide semiconductor (PMOS) transistors M1 and M2 arranged in a current mirror configuration. Similarly, two n-channel MOS (NMOS) transistors M3 and M4 are arranged in another current mirror configuration. The two current mirrors provide charge and discharge (or pump) current, respectively, to the loop filter (not shown). The current corresponding to the charge current mirror (including the PMOS transistors M1 and M2) is designated as Iup, and the current corresponding to the discharge current mirror (including the NMOS transistors M3 and M4) is designated as Idn. Two additional transistors M5 (PMOS) and M6 (NMOS) serve as corresponding switches for the charge and discharge current mirrors. Parasitic capacitances of the MOS switching devices M5 and M6 are designated as Cgsp, Cgdp, Cgsn, and Cgdn. Since the MOS switching devices M5 and M6 are coupled to the drains of the corresponding current mirror transistors, this configuration is generally referred to as a drain-switched current mirror configuration.
The MOS switching devices M5 and M6 are operated by control signals UN and DP that are generated by the PFD (not shown). In this way, the PFD controls the charge pump to charge or discharge the loop filter. When the control signals change from HIGH to LOW or LOW to HIGH, this state transition causes a voltage swing at the charge pump output because of coupling of the parasitic capacitances (i.e., Cgsp, Cgdp, Cgsn, and/or Cgdn) of the MOS switching devices M5 and M6. This voltage swing is called clock feed-through. Also, when the MOS switching devices M5 and M6 are turned off, the charge in the depletion region of the channel will be injected to the load capacitor of the charge pump and cause unwanted voltage swing at the charge pump output. This voltage swing is called charge injection. The spurious noise associated with clock feed-through and charge injection due to the operation of the charge pump decreases the quality of the output signal generated by the PLL circuit.